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JEDEC JESD235C PDF Format

$123.50

High Bandwidth Memory (HBM) Dram (HBM1, HBM2)
standard by JEDEC Solid State Technology Association, 01/01/2020

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Description

The HBM DRAM is tightly coupled to the host compute die with a distributed interface. The interface is divided into independent channels. Each channel is completely independent of one another. Channels are not necessarily synchronous to each other. The HBM DRAM uses a wide-interface architecture to achieve high-speed, low-power operation. The HBM DRAM uses differential clock CK_t/CK_c. Commands are registered at the rising edge of CK_t, CK_c. Each channel interface maintains a 128b data bus operating at DDR data rates.

Product Details

Published:
01/01/2020
Number of Pages:
213
File Size:
1 file , 5.3 MB